1. Field of the Invention
The present invention relates to systems for modeling electronic circuits and, more specifically, to a system for modeling electromagnetic effects in circuits with through silicon vias.
2. Description of the Related Art
After several years of effort on the realization of silicon-based three-dimensional (3-D) integration using through-silicon vias (TSVs), major semiconductor companies have recently started mass production using this technology for field-programmable gate array (FPGA) and flash memory applications. Along with the first success in commercialization through process development, system-level designers are beginning to realize that further progress in performance is possible only with the support of sophisticated design tools based on comprehensive electrical modeling of TSVs. Although existing TSV modeling methods, which provide simple equivalent circuits, have been successfully adopted for initial design validations, they neglect or approximately consider important characteristics required for design optimization.
A major characteristic to be considered for enhancing the functionality of modeling is the effect of depletion region that is formed when a bias voltage is applied to TSVs. Since the depletion region adds another capacitance to the oxide liner, the values of parasitic elements in TSVs are modified. Also, the tunable property of the MOS capacitance can be utilized for adaptive circuit design. For modeling the effect of the TSV depletion capacitance, previous systems applied semiconductor equations to the cylindrical TSV structure. However, such systems focused on the depletion region of a single TSV without considering the interaction between multiple TSVs having depletion regions when constructing an equivalent circuit.
Another characteristic to be included for improving modeling accuracy is the effect of the finite silicon substrate. The substrate effect should be modeled more accurately for TSV interposers since the substrate thickness is becoming smaller due to wafer thinning processes. Current circuit modeling methods handle the effect by applying 2-D formulas to simple partitioned sections, but such methods are not accurate when each section length is small compared to the cross-sectional dimension of TSVs.
Therefore, there is a need for a modeling method for TSVs that includes depletion region modeling of several TSVs and that includes modeling of finite silicon substrates.